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![PDF] A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/4492954219035e0111652e49d71aa2eff9cea775/4-Figure4-1.png "PDF] A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing | Semantic Scholar")
PDF] A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing | Semantic Scholar
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PDF] Design and Analysis of 8 T / 10 T SRAM cell using Charge Recycling Logic | Semantic Scholar
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![Schematic of read and write circuits of the SRAM cell [6] and the... | Download Scientific Diagram](https://www.researchgate.net/profile/Govind-Prasad-6/publication/269577949/figure/fig4/AS:1034855328542721@1623740145218/Schematic-of-read-and-write-circuits-of-the-SRAM-cell-6-and-the-additional-logic-for_Q640.jpg "Schematic of read and write circuits of the SRAM cell [6] and the... | Download Scientific Diagram")
Schematic of read and write circuits of the SRAM cell [6] and the... | Download Scientific Diagram
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![PDF] A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/4492954219035e0111652e49d71aa2eff9cea775/3-Figure2-1.png "PDF] A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing | Semantic Scholar")
PDF] A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing | Semantic Scholar
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